library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity dram is
  port
  (
    clk				:	IN	STD_LOGIC;
    nReset : in std_logic;
    addr      : IN  STD_LOGIC_VECTOR (3 DOWNTO 0);
    we        : IN  STD_LOGIC := '1';
    writeport : IN  STD_LOGIC_VECTOR (74 DOWNTO 0);
    readport  : OUT STD_LOGIC_VECTOR (74 DOWNTO 0)
  );
end dram;


architecture internalRAM of dram is
        type cachestatusbits is array (0 to 15) of std_logic_vector (1 downto 0);
        type cachetag    is array (0 to 15) of std_logic_vector(8 downto 0);
        type cacheword is array (0 to 15) of std_logic_vector(31 downto 0);
        type cacheram is array (0 to 15) of std_logic_vector (74 downto 0);
        
        signal cbits : cachestatusbits;
        signal ctag : cachetag;
        signal cword0, cword1 : cacheword;
        signal cram : cacheram;


begin

        ramreg : process (clk, we, addr, nReset)
        begin
          if (nReset = '0') then
                  for i in 0 to 15 loop
                    cbits(i) <= (others => '0');
                    ctag(i) <= (others => '0');
                    cword1(i)    <= (others => '0');
                    cword0(i)    <= (others => '0');
                        cram(i) <= (others => '0');
                  end loop;
                elsif (rising_edge(clk)) then
                        if (we = '1') then
                                for i in 0 to 15 loop
                                        if (std_logic_vector(to_unsigned(i,addr'length)) = addr) then
                                                cbits(i) <= writeport (74 downto 73);
                                                ctag(i) <= writeport (72 downto 64);
                                                cword1(i)    <= writeport (63 downto 32);
                                                cword0(i)    <= writeport (31 downto 0);
                                                cram(i) <= writeport;
                                        end if;
                                end loop;
                        end if;
                end if;
        end process;

        ramread : process (addr,cbits, ctag, cword1, cword0, cram)
        begin
                readport <= (others => '0');
                for i in 0 to 15 loop
                        if (std_logic_vector(to_unsigned(i,addr'length)) = addr) then
                                readport <= cbits(i) & ctag(i) & cword1(i) & cword0(i);
                        end if;
                end loop;
        end process;

end internalRAM;


